Jeff Pu, an analyst at GF Securities in South Korea, believes that NVIDIA may adopt Foveros packaging technology in the second half of 2028. This news should be viewed with caution, as no relevant contracts or specific products have been announced yet.
This speculation aligns with an early report from DigiTimes in January of this year. The report mentioned that supporting components for NVIDIA's future Feynman series GPUs might use Intel's 18A or 14A processes, while the production of the main GPU chips would still be handled by TSMC's advanced processes.
In other words, Intel will mainly be responsible for non-core IP modules or the backend processes after wafer die manufacturing. The 14A process is scheduled for mass production in the second half of 2028, a timeline that aligns with the one provided by Jeff Pu.
The manufacturing of AI accelerators is divided into front-end and back-end processes: the front-end primarily involves creating circuits on wafers; the back-end includes wafer dicing, interconnection, and integrating various dies into package housings, ultimately producing chips ready for use in data centers.
Intel is still striving to catch up with TSMC in the foundry sector for the most advanced processes. However, in the packaging arena, Intel's EMIB, EMIB-T, and Foveros technologies are relatively mature. It is reported that Google has expressed interest in EMIB-T, planning to use it for its self-developed AI Tensor Processing Units (TPUs).
EMIB uses silicon bridges embedded in the substrate to laterally connect multiple chiplets. EMIB-T builds on this architecture by adding TSVs (Through-Silicon Vias), which are vertical interconnect channels penetrating the silicon wafer to directly transmit power and signals.
Foveros takes it a step further by **vertically stacking** compute dies or other chiplets onto a base die. This structure can reduce the lateral footprint of the package, shorten interconnect lines, and is expected to increase bandwidth and improve energy efficiency.
For NVIDIA, diversifying backend packaging suppliers can reduce reliance on TSMC's packaging capacity, which is currently under significant strain due to strong global demand for AI accelerators.
For Intel, securing the Feynman-related projects holds greater significance in completing the industrial validation of Foveros technology rather than achieving an immediate victory in the advanced lithography race.
Jeff Pu, an analyst at GF Securities in South Korea, believes that NVIDIA may adopt Foveros packaging technology in the second half of 2028. This news should be viewed with caution, as no relevant contracts or specific products have been announced yet.
This speculation aligns with an early report from DigiTimes in January of this year. The report mentioned that supporting components for NVIDIA's future Feynman series GPUs might use Intel's 18A or 14A processes, while the production of the main GPU chips would still be handled by TSMC's advanced processes.
In other words, Intel will mainly be responsible for non-core IP modules or the backend processes after wafer die manufacturing. The 14A process is scheduled for mass production in the second half of 2028, a timeline that aligns with the one provided by Jeff Pu.
The manufacturing of AI accelerators is divided into front-end and back-end processes: the front-end primarily involves creating circuits on wafers; the back-end includes wafer dicing, interconnection, and integrating various dies into package housings, ultimately producing chips ready for use in data centers.
Intel is still striving to catch up with TSMC in the foundry sector for the most advanced processes. However, in the packaging arena, Intel's EMIB, EMIB-T, and Foveros technologies are relatively mature. It is reported that Google has expressed interest in EMIB-T, planning to use it for its self-developed AI Tensor Processing Units (TPUs).
EMIB uses silicon bridges embedded in the substrate to laterally connect multiple chiplets. EMIB-T builds on this architecture by adding TSVs (Through-Silicon Vias), which are vertical interconnect channels penetrating the silicon wafer to directly transmit power and signals.
Foveros takes it a step further by **vertically stacking** compute dies or other chiplets onto a base die. This structure can reduce the lateral footprint of the package, shorten interconnect lines, and is expected to increase bandwidth and improve energy efficiency.
For NVIDIA, diversifying backend packaging suppliers can reduce reliance on TSMC's packaging capacity, which is currently under significant strain due to strong global demand for AI accelerators.
For Intel, securing the Feynman-related projects holds greater significance in completing the industrial validation of Foveros technology rather than achieving an immediate victory in the advanced lithography race.